clock input
英 [klɒk ˈɪnpʊt]
美 [klɑːk ˈɪnpʊt]
网络 时钟输入; 时脉输入
双语例句
- A single clock input is used to control all internal conversion cycles.
采用一个单时钟输入来控制所有内部转换周期。 - Another example is designing a system that gets the date from the internal clock instead of asking for input from users.
另一个例子是设计从内部时钟获取数据的系统，用来取代请求用户输入。 - Bit synchronous clock recover circuit is the key part of the communication system, it can exactly recover the synchronous signal from input data stream.
位同步时钟信号的提取是通信系统中的关键部分，应用数字锁相环可以准确地从输入码流中提取出位同步信号。 - The circadian clock is a self-sustaining oscillator with a period of about 24 hour that includes input, central oscillator and output.
昼夜节律生物钟是一种以近似24小时为周期的自主维持的振荡器，由输人通路、中央振荡器和输出通路三部分组成的。 - When 10 MHz clock frequency is used, the operation time per point is about 4 μ s for the complex signal input sequence of 16 bits in word-length.
对复数输入信号序列，字长16位，时钟速率10MHz时，每点运算时间约4μs，根据对运算速度及设备量的要求，可选用并行或串并行方案。 - A pulse decoded modulation ( PCM) circuit was designed by the use of external clock input of serial data output of analog-to-digital converter.
设计了脉冲编码调制（PCM）线路.利用模数转换芯片的外部时钟输入及串行数据输出。 - It has many kinds of ways for analog input and the clock input, so it's possible to realize the electric circuit plan of multi-purpose data acquisition with the using of these characteristics.
它具有多种模拟输入和时钟输入方式，利用这些特性可实现多功能的数据采集电路方案。 - The VCO module makes use of differential coefficient circuit design technology to lower the effect of power resource on the clock signal input shake.
系统VCO模块采用微分电路设计技术，可将电源噪音对时钟信号输出抖动的影响降至最低。 - This paper present a design of digital clock with two alarms and introduce some circuits concretely such as three input circuit, reversible counter and output decoder/ driver.
简述了一种双闹钟数字时钟芯片的设计分析，具体介绍了其中三态输入电路、可逆计数器、输出解码/驱动器等电路的设计。 - The technology of frequency doubling and phase shifting of FPGA is used to measure accurately the ultrasonic wave transmit-time in the case of low frequency clock input.
为了提高流量计的精度，使用FPGA倍频移相技术在低频时钟的情况下实现了对两个通道的超高频精确计时。 - The genetic amenability of Drosophila has led to the identification of more than ten clock genes and a set of clock-related genes, including clock input and clock-regulated genes.
到目前为止，通过遗传学和生物化学方法已经鉴定到10多个时钟基因（clockgenes）和许多时钟相关基因，包括时钟输入基因和钟控基因。 - These rhythms are regulated by the biological clock, which includes an input pathway, a central oscillator, an output pathway and a gateway.
高等植物的生物钟系统由输入途径、中央振荡器、输出途径以及一个阀门效应器组成。 - Because of the basic feature of self-bias PLL, the ratio of loop bandwidth and reference clock can be kept to be a certain range so that both of the lock time and input tracking jitter can be improved.
因为自偏置锁相环的特点，使得所设计的锁相环的带宽与输入频率的比值可以保持在一个相对稳定的范围，对锁定时间以及输入频率跟踪抖动得到改善。 - The test equipments of PTN device rely on precise clock synchronization technology to support the implementation of input and output data analog for time-division multiplexing services.
PTN网络测试设备在实施时分复用业务数据输出模拟时，需要依靠精确的时钟同步作为技术支撑。 - After the introduction of the clock reference indicators, detailed analyses of the trial system clock input and clock processing circuit, as well as the test results of the clock performance in the trial system are provided.
通过时钟特性指标的介绍，本文详细分析了试验系统的时钟输入和沿路的时钟处理电路，测试了试验系统的时钟性能。 - System hardware design is as follows: the design of memory module, JTAG interface design, the clock system design, power module design, reset circuit design, video input and output module design, alarm circuit design and so on.
系统的硬件设计主要包括：存储器模块的设计、JTAG接口的设计、时钟系统的设计、电源模块的设计、复位系统的设计、视频输入输出模块的设计、报警电路的设计等。 - Clock extraction from degraded NRZ signal was experimental realized. The tolerance of the input signal deterioration degree was analyzed.
实验实现了恶化NRZ信号的时钟提取，分析了该时钟提取结构对输入信号恶化程度的容忍度。 - The design of the system mainly includes the clock circuit design, peripheral memory circuit design, gigabit Ethernet interface design, image sampling input/ output interface design, and so on.
该系统的设计主要包括时钟电路设计、外围存储器电路设计、千兆以太网接口设计、图像采集输入输出接口设计等等。 - Each ACE includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and ( 216-1).
每一个集成异步通信器件包括一个可编程的波特率发生器，它能够对输入时钟进行1～216-1的分频。 - If use the phase-locked loop technology on clock synchronization, the output signal of the clock accuracy and stability directly dependent on the input reference signal.
锁相环是一种让输出信号在频率和相位上与输入参考信号同步的技术，输出信号的时钟准确度和稳定性直接依赖于输入参考信号。